The present invention relates to an improved structure and method of manufacturing of an integrated circuit device including a field effect transistor such as a vertical type static induction transistor (SIT) or a FET.
An SIT has excellent high frequency response characteristics due to a high input impedance, a low output impedance, a low capacitance and a high conversion conductance, and it is well known that an integrated circuit in which it is incorporated has advantages of a high speed operation and a lower power consumption. A vertical structure type SIT has further advantages of high integration density and ease of fabrication. However, there are some problems to be solved with respect to device structure and method of fabrication in order to further improve the characteristics of the device.
In an I.sup.2 L type SITL composed of a planar-gate type SIT and a lateral bipolar transistor, a drain electrode and a gate electrode are conventionally formed almost on the same surface. This planar-gate type SITL can be fabricated by simple steps. However, since the SITL requires the characteristic of a normally off type device, the cross-sectional area of the channel region must be formed small.
Since the high impurity concentration region of the main electrode and the high impurity concentration region acting as a gate are overlapped, the capacitance between them is increased and satisfactory characteristics of the SITL cannot be obtained. In this SITL structure, it is difficult to reduce the minority carrier storage.
As a result, improvement in operational speed and power consumption can not be achieved. To avoid these problems, a step cut type SITL in which the gate is formed on the bottom surface or the side face of the step has been proposed. However, this type of SITL is not always sufficient due to the difficulty of wiring the electrode regions and the fine working required for forming the bottom surface. The problems described above will not occur only in the case of an inverted SIT in an I.sup.2 L type SITL, but also in the case of a so-called vertical-type SIT in which the n.sup.+ source electrode is formed on the major surface, in a P channel SIT, in a normally-on type SIT, and in other types of SIT logic circuits and analog circuit.
Furthermore, problems with the prior art will be hereinafter described by referring to FIG. 1.
FIG. 1 shows the typical example of a conventional planar-gate type SITL of one unit, wherein a planar view thereof (FIG. 1b), a sectional view thereof taken on line A--A' (FIG. 1a) and a sectional view thereof taken on line B--B' (FIG. 1c) are illustrated. The n-channel SIT is composed of a n.sup.+ source region 12 and a n.sup.+ drain region 11 on the side of a n.sup.+ substrate which is a main electrode high impurity density region, a p.sup.+ gate region 14 for a control electrode and a n.sup.- channel region 13, and the lateral BJT is composed of a p.sup.+ emitter region 15, a n.sup.- base region 13a and a p.sup.+ collector region 14. The p.sup.+ collector region and the p.sup.+ gate region 14 are a common region, and the n.sup.+ base region and the n.sup.+ source region 12 are a common region. In the plan view of FIG. 1b, to simplify, a surface oxide film 7 and metal wirings (an emitter electrode 5, the gate electrode 4 and the drain electrode 1) are omitted therefrom. A voltage of a power source is applied to the emitter electrode 5, an input voltage is applied to the gate electrode 4 and an output voltage is derived from the drain electrode 1.
The planar-gate type SITL can be fabricated by a simple series of steps comprising four steps of photo-lithography and two steps of diffusion. However, there is still the following problem. Since this SITL requires the characteristic of a normally off type SIT, a gate-spacing W.sub.G should be less than two times the width of a depletion layer determined in accordance with a diffusion potential and W.sub.G is less than 20 to 2 [.mu.m] when an impurity density of the n.sup.- channel region 13 is between 10.sup.13 and 10.sup.15 [cm.sup.-3 ]. In order to determine a source-drain leakage current at a desired small value when a gate voltage is zero, it is preferable to reduce the dimension W.sub.G and to keep a potential barrier for electrons injected from the n.sup.+ source region 12 away from the n.sup.+ drain region 11. Furthermore, to reduce a source negative feed-back resistance, this potential barrier preferably is taken close to the n.sup.+ source region 12 so that the p.sup.+ gate region should be formed so as to be deep to the same degree. This causes the increase of plane area of p.sup.+ gate region 14, and the p.sup.+ gate region 14 and the n.sup.+ drain region 11 come to overlap each other as shown in FIG. 1 resulting in an increase in the gate-source capacitance and gate-drain capacitance.
In order to reduce the gate-drain capacitance, a fine working technique to attain accurate positioning is required for forming a n.sup.+ diffusion opening with sufficiently small diameter and it is not allowed to form the deeper diffusion region. As a result, a spike phenomenon for electrode metal is liable to occur, and yield is reduced. Moreover, the outer peripheral region of the p.sup.+ gate region 14 is not at all necessary for the operation thereof and holes are injected into the n.sup.- region 13 from the p.sup.+ gate region 14 with an increase of the junction capacitance so that a carrier storage effect becomes more effective.